View JLC1563-D_2957958.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? semiconductor components industries, llc, 2000 june, 2000 rev. 0 1 publication order number: jlc1563/d
jlc1563 is an i2cbus signal transceiver and aconditioner''. currently, systems complexity and i2cbus device types and functionality are only increasing. as a result of i2cbus loading the clock line and data line signals degrade. the jlc1563 i2cbus transceiver restores clean signals in the system leading to improvements in system performance and reliability. this device has two pins, scl1 (serial clock input) and sda1 (serial data i/o), on the master i2cbus side; and two pins, scl2 (serial clock output) and sda2 (serial data i/o), on the slave i2cbus side. two reset pins, reset1 and reset2, drive separate internal comparators and a system poweronreset function is supported. features ? low power dissipation ? two pin reset/poweronreset ? waveform cleaning pdip8 p suffix case 626 1 8 http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week 1 jlc1563p awl yyww marking diagrams 8 device package shipping ordering information jlc1563p pdip8 50 units/rail highperformance cmos lowpower complementary mos silicongate 1 8 soeiaj8 m suffix case 968 1 8 1563 alyw jlc1563m soeiaj8 see note 1. jlc1563ml1 soeiaj8 see note 1. 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative.
jlc1563 http://onsemi.com 2 pin list scl 1 scl 2 sda 1 master serial data master serial clock slave serial clock sda 2 reset 1 reset input 1 (active low) slave serial data reset 2 reset input 2 (active low) pin connections 1 reset 1 8 v dd 2 scl 1 3 sda 1 4 gnd 7 reset 2 6 scl 2 5 sda 2 case 626/968 block diagram comp comp poweron reset i 2 c bus controller scl to master reset 1 reset 2 sda to master scl to slave sda to slave
jlc1563 http://onsemi.com 3 maximum ratings (v ss reference) rating symbol value unit dc supply voltage v dd 0.5 to +7.0 v dc input voltage v in 0.5 to v dd + 0.5 v dc output voltage v out 0.5 to v dd + 0.5 v dc input output current (per pin) i 25 ma dc supply current (v dd and gnd pin) i dd 75 ma storage temperature t stg 65 to +150 c lead temperature (1 mm from case for 10 sec) t l 300 c recommended operating conditions parameter symbol min max unit dc supply voltage v dd 4.0 6.0 v dc input voltage v in 0.0 v dd v operating temperature t a 40 +85 c dc characteristics (v ss reference) guaranteed limits characteristic symbol min max unit input voltage ah'' level v ih 0.7 v dd v input voltage al'' level v il 0.3 v dd v output voltage al'' level i out = 4 ma v ol 0.3 v input leakage current v in = v dd or v ss i in 1.0 m a tristate leakage current output = high impedance; v out = gnd i oz 5.0 m a offset voltage (reset 1, reset 2) v io 0.1 v input pin capacitance c in 10 pf output pin capacitance c out 15 pf in/out pin capacitance c i/o 15 pf quiescent supply current (per package) i cc 5.0 ma
jlc1563 http://onsemi.com 4 sda scl micro controller (master device) i 2 c bus transceiver scl1 sda1 scl2 sda2 slave devices unit 1 i 2 c bus transceiver scl1 sda1 scl2 sda2 slave devices unit 2 i 2 c bus transceiver scl1 sda1 scl2 sda2 other units slave devices application block <> a s 9 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 1 p address data (i) 0 9 8 7 6 5 4 3 2 1 data (ii) on off scl from master sda from master sda from slave from master to slave from slave to master sa sa s i 2 c bus transceiver signals
jlc1563 http://onsemi.com 5 9 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 1 9 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 1 a s p address data (i) 1 data (ii) on off scl from master sda from master sda from slave from master to slave from slave to master s a m <> a s p address data (i) 0 data (ii) on off scl from master sda from master sda from slave from master to slave from slave to master sa sa s reset 1 off on <> i 2 c bus transceiver signals i 2 c bus transceiver signals (during reset)
jlc1563 http://onsemi.com 6 a m 9 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 19 8 7 6 5 4 3 2 1 a s p address data (i) 1 data (ii) on off scl from master sda from master sda from slave from master to slave from slave to master s 1 off on reset <> i 2 c bus transceiver signals (during reset) bus condition key: s = start sa = slave acknowledge ma = master acknowledge p = stop
jlc1563 http://onsemi.com 7 i 2 c bus standards (see switching chart for actual device parameters) guaranteed limits parameter symbol min max unit scl clock frequency f cl 0 100 khz stop condition to start condition bus free time t buf 4.7 m s start condition hold time t hd:sta 4.0 m s scl clock low hold time t low 4.7 m s scl clock hi hold time t high 4.0 m s sda data hold time t hd:dat 0 m s sda data setup time t su:dat 250 ns sda and scl signal rise time t r 1000 ns sda and scl signal fall time t f 300 ns stop condition setup time t su:sto 4.0 m s sda scl t buf t low t r t f t hd:sta t hd:dat t high t su:dat t su:sto
jlc1563 http://onsemi.com 8 switching chart (v cc = 5.0 v, t r = 1000 ns, t f = 300 ns) nominal guaranteed limits parameter symbol nominal 25 c min max unit maximum delay scl1 to scl2 t phl:scl 500 ns maximum delay scl1 to scl2 t plz:scl 500 ns maximum delay sda1 to sda2 t phl:sda 500 ns maximum delay sda1 to sda2 t plz:sda 500 ns maximum delay scl1 to sda1,2 (direction change data = l) t phl:sclsda 500 ns maximum delay scl1 to sda1,2 (direction change data = h) t plz:sclsda 500 ns maximum delay reset to sda1,2 t plz:res 500 ns maximum output fall time scl t thl:scl 5.0 20 ns maximum output rise time sda t thl:sda 5.0 20 ns maximum group delay tphl:scltphl:sda t phl 1.0 10 ns maximum group delay tplz:scltplz:sda t plz 1.0 10 ns power on reset pulse width t w:ror 1500 ns timing conditions (v dd = 5.0 v) nominal guaranteed limits parameter symbol nominal 25 c min max unit minimum pulse width reset t w:res 50 ns
jlc1563 http://onsemi.com 9 (1) t phl:scl , t plz:scl , t phl:sda , t plz:sda , t thl:scl , t thl:sda (2) t phl:sclsda , t plz:sclsda 90% 50% 10% 90% 50% 10% 90% 50% 10% 10% 10% 50% 90% 50% 10% 10% t t data = h data = l t t t t t t t (3) t plz:res input scl1 / sda1 output scl2 / sda2 input scl1 output sda1, sda2 input reset1 / reset2 output sda1, sda2 fr phl plz thl f phl, t plz f plz
jlc1563 http://onsemi.com 10 (4) t w:por , t w:res test circuit scl2 sda2 50 pf 50 pf 2.5 k 2.5 k t w:res t w:por t w:por v dd < 1.5 v v dd por (internal) t > 2 m s reset 1,2
jlc1563 http://onsemi.com 11 package dimensions e 0.10 (0.004) dim a min max min max inches 2.05 0.081 millimeters a 0.05 0.20 0.002 0.008 b 0.35 0.50 0.014 0.020 c 0.18 0.27 0.007 0.011 d 5.10 5.50 0.201 0.217 e 5.10 5.45 0.201 0.215 e 1.27 bsc 0.050 bsc h 7.40 8.20 0.291 0.323 l 0.50 0.85 0.020 0.033 l 1.10 1.50 0.043 0.059 m 0 10 0 10 q 0.70 0.90 0.028 0.035 z 0.94 0.037 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter 3. dimension d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot minimum space between protrusions and adjacent lead to be 0.46 (0.018). 1 e e 1 z d e h e 14 5 8 b 0.13 (0.005) m a 1 a c m l e l q 1 detail p p soeiaj8 m suffix case 96801 issue o pdip8 p suffix case 62605 issue k notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 a b t seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m 10 10 n 0.76 1.01 0.030 0.040
jlc1563 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent r ights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. jlc1563/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (mf 1:00pm to 5:00pm munich time) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (mf 1:00pm to 5:00pm toulouse time) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (mf 12:00pm to 5:00pm uk time) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, england, ireland

▲Up To Search▲

Price & Availability of JLC1563-D

	To Download JLC1563-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .